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ASE Group Unveils TSV-Enhanced Packaging as Chipmakers Chase AI Efficiency

The company targets higher bandwidth demands in competitive advanced packaging market
Taiwan
a 3711.TW Blue Chip 150 OM 60 Semicon 75 Tech 350
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Taiwan’s ASE Technology Holding Co. introduced an enhanced version of its chip packaging technology that incorporates through-silicon vias, the latest effort by the world’s largest outsourced semiconductor assembly provider to capture a bigger share of the lucrative artificial intelligence chip market.

The company announced its FOCoS-Bridge technology with TSV capabilities, designed to address growing bandwidth requirements in AI and high-performance computing applications. The integration creates shorter transmission paths and enables higher input-output density with improved thermal management, according to the Kaohsiung-based company.

The announcement represents an incremental improvement to ASE’s existing VIPack platform rather than a breakthrough innovation. TSV technology has been widely used in applications from high-bandwidth memory to CMOS image sensors, with the market facing ongoing challenges around manufacturing costs and process complexity.

ASE commands about 19% of the global OSAT market and has been working to differentiate its offerings as competition intensifies from Chinese rivals including JCET Group and Tongfu Microelectronics. The company faces pressure as less than 20% of data center capacity used advanced 2.5D packaging in 2022, though adoption could reach 50% within five years.

Executive Vice President Yin Chang said the technology addresses exponential growth in computational requirements across applications from autonomous vehicles to medical diagnostics. The company emphasized energy efficiency benefits as power consumption becomes increasingly critical for AI applications.

The TSV packaging market faces headwinds from high manufacturing costs and design complexity, though demand continues growing for miniaturized devices. ASE’s latest offering comes as the industry grapples with Moore’s Law limitations and seeks alternative approaches to boost chip performance.

The company will showcase the technology at the Electronic Components and Technology Conference in Dallas this week, as it competes with Taiwan Semiconductor Manufacturing Co.’s CoWoS platform and Intel’s EMIB technology for advanced packaging contracts.

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