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Samsung Electronics Advances in Panel Level Packaging, Surpassing TSMC

Strategic acquisition and technological developments position Samsung as a leader in semiconductor packaging
South Korea
s 005930.KO t 2330.TW Blue Chip 150 OM 60 Semicon 75 Tech 350
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Samsung Electronics is making significant strides in the semiconductor packaging industry, positioning itself ahead of TSMC in the Panel Level Packaging (PLP) field. This progress follows Samsung’s strategic acquisition of the PLP business from Samsung Electro-Mechanics in 2019 for 785 billion won ($581 million), laying the groundwork for its current advancements.

At a shareholders’ meeting in March, Kyung Kye-hyun, former head of Samsung Electronics’ semiconductor division, emphasized the importance of PLP technology. He explained that AI semiconductor dies, often measuring 600mm x 600mm or 800mm x 800mm, necessitate advanced packaging technologies like PLP. Samsung is actively developing and collaborating with clients on this front.

TSMC, meanwhile, has encountered setbacks. Construction of its CoWoS packaging plant in southwestern Taiwan was halted due to the discovery of historical relics, exacerbating existing bottlenecks in its “Chip on Wafer on Substrate” (CoWoS) technology. TSMC’s recent entry into PLP research, including Fan-Out (FO)-PLP, marks a significant shift despite its initial skepticism.

According to Nikkei Asia, TSMC’s PLP research is in early stages, with mass production expected to take several years. This shift is seen as a response to chronic bottlenecks in CoWoS technology, which currently struggles to meet the demands of clients like NVIDIA. Market research firm IDC reports that NVIDIA requires half of TSMC’s CoWoS capacity for its AI semiconductors, but only about one-third is currently secured.

The competition in PLP technologies is intensifying. DigiTimes reports that NVIDIA plans to adopt FO-PLP for server AI semiconductors due to TSMC’s packaging supply constraints. TrendForce, a Taiwanese market research firm, highlights PLP as a new battleground for TSMC, Samsung, and Intel.

Samsung offers FO-PLP for low-power memory integration applications, such as mobile and wearable devices, and plans to expand its 2.5D packaging technology, I-Cube, to include PLP. Intel also aims to mass-produce advanced packaging solutions using glass substrates between 2026 and 2030, marking an industry first.

As competition heats up, Samsung’s early adoption and development in PLP could solidify its leadership in the semiconductor packaging market.



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