Taiwan Semiconductor Manufacturing Co. disclosed new details about its upcoming 2-nanometer chip technology, highlighting performance improvements over its current 3nm process. The world’s largest contract chipmaker said the new node will deliver up to 15% faster speeds or 35% better energy efficiency while increasing transistor density by 15%.
The advances stem from TSMC’s shift to gate-all-around nanosheet transistors, moving away from the FinFET architecture used in previous generations. According to company R&D chief Geoffrey Yeap, the technology represents over four years of development work.
The new design allows for more precise control over current flow by using stacked silicon ribbons instead of vertical fins. This enables chip designers to fine-tune performance by adjusting nanosheet widths – a flexibility not possible with FinFETs.
TSMC has also achieved breakthrough improvements in SRAM density, reaching 38 megabits per square millimeter. This marks an 11% gain over the 3nm process, addressing a long-standing bottleneck in processor memory scaling.
While TSMC prepares for mass production next year, rival Samsung has faced reported difficulties with yields on its own 3nm GAA process. The Korean firm’s challenges have reportedly impacted its ability to manufacture next-generation Exynos mobile chips.
