SK Hynix outlined ambitious plans to overhaul memory chip technology over the next 30 years, presenting unproven approaches at a Kyoto semiconductor conference as the industry grapples with fundamental physics constraints.
The South Korean chipmaker, which recently overtook Samsung as the world’s largest DRAM supplier, proposed transitioning to 4F² Vertical Gate platforms for chips at 10-nanometer nodes and below. The company also highlighted 3D DRAM as a cornerstone technology alongside the vertical gate approach.
The presentation comes as DRAM cell capacitance has decreased to below 10 femtofarads per cell at current technology nodes, with industry experts warning that 10 nanometers may represent the final scaling generation for conventional 6F² cell designs. Memory manufacturers face mounting challenges including wordline-to-wordline coupling and bitline-to-bitline coupling in advanced transistor structures.
SK Hynix captured 36% of global DRAM revenue in the first quarter, driven primarily by its 70% dominance in high-bandwidth memory used in artificial intelligence servers. The company’s newfound market leadership stems largely from AI-driven demand rather than manufacturing breakthroughs in conventional memory.
While acknowledging industry concerns about rising costs from layer stacking in 3D architectures, SK Hynix maintains that continuous innovation will keep scaling economically viable. The company provided few technical details about implementation timelines or manufacturing feasibility for its proposed technologies.
