Taiwan Semiconductor Manufacturing Co. (TSMC) confirmed it is investigating a groundbreaking chip packaging technology for artificial intelligence, though it warned that production constraints for AI chips will persist until 2025. This projection extends previous expectations.
TSMC has allocated between $30 billion and $32 billion for capital expenditures in 2024, aimed at boosting advanced chip production and packaging capabilities. Chairman and CEO C.C. Wei noted the company’s exploration of panel fan-out technology, which could mature in three years. This method uses rectangular substrates instead of traditional round wafers, potentially revolutionizing chip assembly and packaging.
Despite robust demand for AI chips, TSMC’s advanced packaging technology, CoWoS, remains under capacity constraints. CoWoS is crucial for integrating high-performance components like graphics processors and high-bandwidth memory. Wei emphasized the ongoing efforts to increase capacity, with plans to double CoWoS capacity again next year.
TSMC’s roadmap includes mass production of its 2-nanometer technology by late 2025 and an advanced 1.6-nm node by 2026. The AI boom is expected to expand from cloud servers to edge devices, potentially shortening the replacement cycle for smartphones and PCs.
TSMC continues to supply leading global chip developers, including Nvidia, AMD, and Intel, and is the sole supplier of processors for Apple’s upcoming iPhone. The company is considering price increases for its advanced chip production, with analysts predicting a 5-10% hike starting January 2025 due to rising costs and increasing project complexity.
