Taiwan Semiconductor Manufacturing Co. is preparing to establish an experimental production line for fan-out panel-level packaging (FOPLP) by 2026, deepening its collaboration with ASE Technology Holding Co., according to industry sources familiar with the matter.
TSMC plans to align its initial substrate specifications with ASE’s existing 300×300 millimeter format, rather than the previously reported 515×510 millimeter size. The move could accelerate yield improvement and avoid cutting-related challenges, the sources said.
ASE, the world’s largest chip packaging company, has been developing panel-level packaging solutions for over five years. The company’s Chief Operating Officer Tien-Yu Wu indicated that panel-level packaging equipment could be ready as early as the second quarter of 2025.
TSMC Chairman Mark Liu previously stated that FOPLP technology needs at least three years to mature. The chipmaker declined to comment on the latest developments, but in June acknowledged monitoring panel-level packaging advancements.
The partnership signals Taiwan’s push to strengthen its advanced packaging capabilities as competition intensifies in the global semiconductor industry.
